Fin-type field effect transistors (FinFETs) have emerged as an effective approach to support the scaling of integrated circuits, as FinFETs require less area than planar transistors. FinFETs utilize fin structures of semiconductor material that function as channels for the FinFETs. Fin structures may be formed in logic areas and memory areas on a semiconductor substrate through general semiconductor patterning processes.
The continued scaling of integrated circuits has generated a demand for methods for forming nanometer-sized features, such as fin structures, that are separated by nanometer-sized distances. As the limits of optical resolution are approached in current lithography processes, double patterning processes have been used to create critical dimensions (CD) and spaces that are beyond the capability of a single lithography step. Specifically, while a conventional lithographic process can be used to form a line-width equal to a minimum critical dimension associated with the lithographic process, a double patterning process can be used to form a line-width smaller than the minimum critical dimension. Double patterning techniques include “pitch split” (also called litho-etch litho-etch, or LELE) and self-aligned double patterning (SADP), also called sidewall image transfer (SIT).
To obtain even smaller feature sizes, self-aligned quadruple patterning (SAQP) or double SIT techniques have been proposed for planar transistors. In some implementations, however, the use of self-aligned quadruple patterning to form fin structures is problematic because only a uniform-pitch layout can currently be achieved. That is, when using SAQP, each fin is spaced apart from each adjacent fin by the same distance. However, while fin structures in a logic area and fin structures in an NMOS portion of an SRAM may be formed with a uniform pitch, and thus current SAQP techniques are suitable, fin structures in a PMOS portion of an SRAM typically require a different pitch or pitches. In other words, if a single fin structure formation process is used to form the fin structures on a semiconductor substrate, the process may be required to form variably spaced fin structures, which current SAQP procedures cannot achieve.
Accordingly, it is desirable to provide methods for fabricating integrated circuits that provide for variably spaced structures. In addition, it is desirable to provide methods for fabricating integrated circuits that use self-aligned quadruple patterning processes to form variably spaced semiconductor fin structures. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.